为 400 G 超大数据中心服务的 DesignWare 56G Ethernet PHY IP

This demo features Synopsys’ DesignWare 56G Ethernet PHY IP showing a robust eye and exceeding the standards’ jitter performances. Synopsys’ 56G Ethernet PHY IP is available in 16-nm and 7-nm FinFET processes, and targets 400G hyperscale data center SoCs.